1 mitsubishi digital assp ? m66010fp/gp 24-bit i/o expander mitsubishi digital assp ? m66010fp/gp 24-bit i/o expander description m66010 semiconductor integrated circuit inputs 24-bit data in series and outputs it in parallel and vice versa, using shift register function. equipped with 2 independent shift registers, one for serial-to- parallel, the other for parallel-to-serial, this ic is able to read serial input data into a shift register while converting data from parallel to serial. parallel input/output pins are set to in- put or output according to the bit. the m66010 is useful in a wide range of applications, such as mcu (micro controller unit) input/output port extension and serial bus system data communication. features ? two-way serial data communication with mcu ? serial data intake possible during parallel-to-serial conver- sion ? parallel input/output switchable according to the bit ? low power dissipation: 100 m w maximum per package (v cc =5v, ta = 25?c, quiescent) ? schmidt input (di, clk, s, cs) ? open drain output (do, d1 thru d24) ? parallel data input and output (d1 thru d24) ? wide operating supply voltage range (v cc = 2v ~ 6v) application mcu-related serial-parallel data conversion, serial bus con- trol by mcu, etc. function the m66010 is produced by using the silicon gate cmos (complementary metal-oxide semiconductor) technology. it is distinguished for low power dissipation and high noise resis- tance. because two independent shift registers are built in, one for serial-to-parallel, the other for parallel-to-serial, this ic is able to read serial input data into a shift register while converting parallel data into serial data. one cycle of latching 24-bit parallel data and outputing it in series while taking in serial data from mcu is initiated by css shift from h to l. at cs fall edges, 24-bit parallel data is latched, and output in series from pin do synchronously with shift clock fall edges. at shift clock rise edges, serial data is taken in from mcu via pin di. the data is read into shift reg- ister. the 25th and following shift clock pulses are ignored and read-in operation is masked. the pin d0 status shifts to high-impedance. as cs is then shifted from l to h, 24-bit serial data taken in via pin di is output in parallel to pins d1 thru d24. because parallel output pins are the n-channel open drain output type, write data h for pins which should be set to input. pin configuration (top view) operation (1) when power is turned on, the status of pins d0 and d1 thru d24 is unstable. their status turns high-impedance when s is shifted to l. (2) at cs fall edges, the status of pins d1 thru d24 is loaded on shift register 1. (3) at clk fall edges, 24-bit data loaded as described above is output in series from pin d0. (4) at clk rise edges, 24-bit serial data is taken in from pin di and written on shift register 2. (5) the 25th and following clk pulses are ignored, and serial data write is discontinued. pin d0 status turns high-imped- ance. (6) at cs rise edges, data written as described in (4) is output to pins d1 thru d24. (7) shift register 1 loads data added from outside as well as and tie data which has the same contents as data latched by serial output latch. (8) if the cs rises before clk reaches the 24th bit, parallel output latch latches data which has been written on shift register, and output it to pins d1 thru d24. (9) pins d1 thru d24 are switched between input and output according to serial data input to pin di. pins for which h is written are set to input. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d0 d1 clk cs v cc s gnd d24 d23 d22 d21 d20 d19 d18 d17 gnd do di clk cs s d24 d23 d22 d21 d20 d19 d18 d17 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 serial data output serial data input clock input chip select input set input parallel data i/o parallel data i/o 32p2w-a 32p2u-b outline
2 mitsubishi digital assp ? m66010fp/gp 24-bit i/o expander block diagram operation timing chart do1 do2 do3 do4 do5 do6 do7 do8 do9 do23 do24 di1 di2 di3 di4 di5 di6 di7 di8 di9 di23 di24 di1 d01 di2 d02 di24 d024 (1) (2) (4) (3) (5) (6) 1 2 3 4 5 6 7 8 9 10 23 24 25 s cs clk di do d1 d2 d24 high impedance one cycle h l 3 6 4 2 7 16 8 9 10 30 31 32 1 5 clk s cs di d24 d23 d22 d3 d2 d1 do d24 d23 d22 d3 d2 d1 q24 q23 q22 q3 q2 q1 d24 d23 d22 d3 d2 d1 q24 q23 q22 q3 q2 q1 di v cc do control circuit clock input set input chip select input serial data input shift register 1 parallel output latch shift register 2 serial data output parallel data i/o gnd gnd input type output type v cc v cc v cc do d1~d24 clk s cs di
3 mitsubishi digital assp ? m66010fp/gp 24-bit i/o expander conditions v i <0v v i >v cc v o <0v v o >v cc gnd ratings C0.5 ~ +7.0 C0.5 ~ v cc + 0.5 C0.5 ~ v cc + 0.5 C20 20 C20 20 C150 C65 ~ 150 symbol v cc v i v o i ik i ok i gnd t stg parameter supply voltage input voltage output voltage input protection diode current output parasitic diode current gnd current storage temperature unit v v v ma ma ma ?c absolute maximum ratings (t a = C20 ~ 75 c unless otherwise noted) recommended operating conditions symbol v cc v i v o t opr parameter supply voltage input voltage output voltage operating temperature limits min. 2 0 0 C20 typ. max. 6 v cc v cc 75 unit v v v c symbol v t+ v tC v ih v il v ol i o i ih i il i cc parameter upper threshold voltage lower threshold voltage high-level input voltage low-level input voltage open drain low-level output voltage output leakage current high-level input leakage current low-level output leakage current static power dissipation electrical characteristics (v cc = 2 ~ 6v unless otherwise noted) limits max. 0.8 v cc 0.65 v cc 0.25 v cc 0.5 10.0 C10.0 1.0 C1.0 200.0 min. 0.35 v cc 0.2 v cc 0.75 v cc max. 0.8 v cc 0.65 v cc 0.25 v cc 0.4 1.0 C1.0 0.1 C0.1 20.0 typ. clk, cs, s, di d1 ~ d24 i ol =5ma v o =v cc v o =gnd unit v v v v v m a m a m a m a min. 0.35 v cc 0.2 v cc 0.75 v cc test conditions v o =0.1v, v cc C0.1v |i o |=20 m a v o =0.1v, v cc C0.1v |i o |=20 m a v o =0.1v, v cc C0.1v |i o |=20 m a v o =0.1v, v cc C0.1v |i o |=20 m a v i =v t+ , v tC v cc =4.5v v i =v t+ , v tC v cc =6v v i =v cc v cc =6.0v v i =gnd v cc =6.0v v i =v cc , gnd v cc =6.0v ta=25?c ta= C20~75?c symbol f max t plz t pzl t plz t pzl t plz parameter input clock maximum repetitive frequency lCz and zCl outputs propagation time clk-do lCz and zCl outputs propagation time cs-d1 to d24 lCz outputs propagation time s=do, d1 to d24 switching characteristics (v cc = 5v) unit mhz ns ns ns ns ns limits max. 400 400 400 400 400 min. 1.9 max. 300 300 300 300 300 typ. min. 2.5 c l =50pf r l =1k w (note) ta=25?c ta= C20~75?c test conditions
4 mitsubishi digital assp ? m66010fp/gp 24-bit i/o expander timing conditions (v cc = 5v) limits note: test circuit (1)pulse generator (pg) characteristics: t r =t f =6ns (10% ~ 90%) (2) capacitance c l includes connection floating capacitance and probe input capacitance. symbol t w t su t h t rec parameter clk, cs and s pulse width di setup time (in response to clk) cs setup time (in response to clk) di thru d24 setup time (in response to cs) di hold time (in response to clk) cs hold time (in response to clk) d1 thru d24 hold time (in response to cs) cs recovery time (in response to s) unit ns ns ns ns max. min. 260 130 130 130 130 130 130 130 max. typ. min. 200 100 100 100 100 100 100 100 test conditions ta=25?c ta= C20~75?c input v cc v cc rl dut p.g. 50 w gnd c l do, d1~d24
5 mitsubishi digital assp ? m66010fp/gp 24-bit i/o expander timing charts clk do cs d1~d24 s do d1~d24 di clk d1~d24 cs s cs v cc gnd v ol v cc gnd v ol v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd 50% 50% 50% 50% 10% 50% 10% 50% 50% 50% 50% 50% 10% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% cs clk tw tw t plz t pzl t plz t pzl tw tw tw t plz t su t h t su t h t su t h t rec v ol
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